How the gates are built

The circuit follows the structure of the equation exactly as written (nothing is simplified). Identical sub-expressions share one gate, and each variable's inverter is drawn once and fanned out.

• NAND only: NOT = 1 NAND (inputs tied together) · AND = 2 NAND (a NAND followed by a NAND-NOT) · OR = 3 NAND (a NAND-NOT on each input, then one NAND).
• NOR only: NOT = 1 NOR (inputs tied together) · OR = 2 NOR (a NOR followed by a NOR-NOT) · AND = 3 NOR (a NOR-NOT on each input, then one NOR).
• Every gate has exactly two inputs. A product or sum of three or more terms is built as a chain, for example ABC = (AB)C, so an n-term AND costs 2(n-1) NAND and an n-term OR costs 3(n-1) NAND (NOR-only: OR 2(n-1), AND 3(n-1)).
• The label under a gate shows the part of the equation completed at that gate. In NAND-only and NOR-only mode only the gate that finishes a part (such as the last NAND of an AND) is labelled, not the helper gates before it.
• In NAND-only or NOR-only mode, XOR and XNOR are first written as XY' + X'Y and XY + X'Y'.