Scenario Strategy:
CPU Instruction Fetch Cycle (Manual Interleaving)
âšī¸ Click Step to simulate context switches
T1: Producer
READY
CPU Reg R1 (Local):
NULL
T2: Consumer
READY
CPU Reg R2 (Local):
NULL
Execution Trace Log
System State & Shared Memory
Shared Heap Variables
shared_count 0
Bounded Buffer (Size 3)
OS Kernel Semaphores
mutex
1
empty
3
full
0
Instruction Breakdown Rules
High-level variables like
1. LOAD memory to register
2. ADD/SUB on register
3. STORE register to memory
Context switching during these 3 steps creates race conditions.
count++ are not atomic. They require 3 CPU steps:1. LOAD memory to register
2. ADD/SUB on register
3. STORE register to memory
Context switching during these 3 steps creates race conditions.