Exam Input Controller
Hardware Cache & MMU State Matrix
IDLE
-- --
Directory Idx (10b)
-- --
Page Table Idx (10b)
-- --
Offset (12b)
Translation Lookaside Buffer (TLB)Fast Path
| Valid | Tag (VPN) | Data (PFN) |
|---|
Level 1: Page Directory PointerOuter Pointer
| Dir Index (Hex / Dec) | Page Table Base Frame | Present bit |
|---|
Level 2: Target Page Table Page entriesInner Pointer
| Table Index (Hex / Dec) | Physical Frame (PFN) | Present bit |
|---|
Mathematical Computation Engine
Exam Mathematical Breakdown
In examinations, virtual memory evaluation questions expect you to isolate individual instruction groupings cleanly from hex formats.
Bit Shifting Rules:
• Directory Index = (VA >> 22) & 0x3FF
• Page Table Index = (VA >> 12) & 0x3FF
• Offset = VA & 0xFFF
• Directory Index = (VA >> 22) & 0x3FF
• Page Table Index = (VA >> 12) & 0x3FF
• Offset = VA & 0xFFF
The remaining 12 bits are preserved cleanly without conversions to formulate the page entry Offset. The final physical address is computed by tracking the mapped Page Frame Number (PFN), shifting it into position, and completing an OR gate configuration sequence against the original structural Offset.